1. Field of the Invention
The present invention relates to a power integrated circuit, and more particularly to a self-isolated power integrated circuit provided with a semiconductor device such as a vertical double-diffused MOSFET (VDNOS) in which low on-state resistance is realized.
2. Description of the Related Art
Conventional high-output power integrated circuits (ICs) can be roughly classified into three types. The first type is a self-isolated power IC described in, for example, "Smart SIPMOS Technology", J. Tihany, Siemens Forsh. -u. Entwickl. -Ber. Bd17 (1988), Nrl, pp. 35-42.
The second type is a junction-isolated power IC described in, for example, "Smart Power Motor Driver for Low Voltage Applications", D. Cave et al., IEEE 1987 Custom Integrated Circuits Conference, pp. 276-279, 1987.
The third type is a dielectrically-isolated power IC described in, for example, "Dielectrically Isolated Intelligent Power Switch", Y, Ohata and T. Isumita, IEEE 1987 Custom Integrated Circuits Conference, pp. 443-446, 1987.
Of these three types of power ICs, the self-isolated power IC to which the present invention is applied will be described with reference to FIG. 3. An n.sup.+ -type substrate 2 has a drain electrode 110 on the bottom surface and an n.sup.- -type epitaxial layer 3 on the top surface. A VDMOS surface structure 11 on n.sup.- -type epitaxial layer 3 includes channel layers 51, sources 81, a gate insulating layer 6, a gate electrode 71, an inter-layer insulation layer 9, a field insulating layer 4, and a source electrode 101.
A PMOS device 12 on n.sup.- -type epitaxial layer 3 includes a source layer 52, a drain layer 53, a gate insulating layer 6, a gate electrode 72, a source electrode 102, and a drain electrode 103.
A NMOS device 13 includes a P-well 54, a source layer 82, a drain layer 83, a gate electrode 73, a drain electrode 104, and a source electrode 105.
A diode 14 on n.sup.- -type epitaxial layer 3 includes an anode layer 55, a cathode-layer 84, an anode electrode 106, and a cathode electrode 107.
By using a silicon wafer as a raw material which is obtained by forming a lightly doped n.sup.- -type substrate 3 through an epitaxial growth technique, the self-isolated power IC as shown in FIG. 3 is produced, for example, through the following steps (1)-(8).
(1) After formation of field insulating layers 4 through thermal oxidation, windows are formed in the field insulating layers 4 through photolithography and etching. PA1 (2) Boron ion injection and thermal diffusion are performed by a photoresist patterned through photolithography to form source layers 52 and drain layer 53 of P-channel MOSFET (PMOS) 12, P well 54 of N-channel MOSFET (NMOS) 13, and anode layer 55 of diode 14. PA1 (3) After formation of gate insulating layers 6 through thermal oxidation, polycrystalline silicon is deposited on gate insulting layers 6 through a Chemical Vapor Deposition (CVD) method, phosphorous ions are injected into the deposited silicon, the silicon is heat-treated so that doping is made to form n.sup.+ -type conductive regions 71, 72 and 73, and, concurrently, a gate electrode 71 of VDMOS surface structure 11, gate electrode 72 of PMOS 12, and gate electrode 73 of NMOS 13 are formed through photolithography and etching. PA1 (4) channel layers 51 are formed through boronion injection and heat treatment by photoresist masks patterned through photolithography. PA1 (5) Similarly, source layers 81 of VDMOS surface structure 11, source layer 82 and drain layer 83 of NMOS 13, and cathode layer 84 of diode 14 are simultaneously formed through arsenic ion injection and heat treatment by photoresist masks patterned through photolithography. PA1 (6) PSG (phosphorus glass) is deposited through a CVD method and windows are formed in the deposited glass through photolithography and etching to form inter-layer insulation layers 9. PA1 (7) Aluminum is deposited with a sputtering method and the deposited aluminum is patterned through photolithography and etching to form a source electrode 101 of VDMOS surface structure 11, source electrode 102 and drain electrode 103 of PMOS 12, source electrode 105 and drain electrode 104 of NMOS 13, and anode electrode 106 and cathode electrode 107 of diode 14. PA1 (8) Finally, drain electrode 110 of VDMOS surface structure 11 is formed through metal evaporation.
For simplicity of description, only an outline of the process steps have been described. It is possible for a process to use additional diffusion layers or wiring layers. Further, it is possible to produce semiconductor devices other than the example shown in FIG. 3.
The power IC illustrated in FIG. 3 may constitute a drive circuit, a protection circuit, a control circuit, etc. by use of PMOS 12, NMOS 13, and diode 14, and can be used as a high-breakdown voltage and large-current power IC by use of a VDMOS, including VDMOS surface structure 11, as an output device.
The self-isolation type power IC tends to be less expensive than either the junction-isolated type or the dielectrically-isolated type, because both the junction-isolated and dielectrically-isolated types involve a relatively large number of complicated process steps to manufacture. The conventional self-isolated type power IC, however, tends to have a high on-state resistance. An explanation for the high on-state resistance of the self-isolated type power IC is given below.
FIG. 4 is an enlarged sectional view showing the VDMOS, including VDMOS surface structure 11, of FIG. 3. In FIG. 4, the on-state resistance R.sub.on of the VDMOS is expressed primarily as the sum of a resistance R.sub.ch at a channel portion, a resistance R.sub.JFET due to the pinch-off effect of the n.sup.- -type epitaxial layer sandwiched between channel layers 51, and a resistance R.sub.epi due to the n.sup.- -type epitaxial layer: EQU R.sub.on =R.sub.ch +R.sub.JFET +R.sub.epi ( 1)
Expression (1) is explained in detail in, for example, "Optimum Design of Power MOSFET'S", C. Hu, et al., IEEE Trans. Electron Devices, vol. ED-31, No. 12, pp. 1693-1700, 1984.
In expression (1), the resistance R.sub.epi of the n.sup.- -type epitaxial layer is substantially proportional to the resistivity .rho. and thickness t.sub.2 of the n.sup.- -type epitaxial layer and can be expressed with a proportional constant a: EQU R.sub.epi =a.multidot..rho..multidot.t.sub.2 ( 2)
Taking the foregoing into consideration, the cause of the high on-state resistance of the conventional self-isolated power IC shown in FIG. 3 will now be further explained.
The isolation breakdown voltage of the circuit of FIG. 3 is determined by the device with the lowest breakdown voltage. Thus, the isolation breakdown voltage of each semiconductor device used in the circuit shown in FIG. 3 (the breakdown voltage against the drain electrode 110 of the VDMOS) must be not lower than the rated (assigned) breakdown voltage of the power IC. Let the breakdown voltage of the VDMOS, the isolation breakdown voltage of PMOS 12, and the isolation breakdown voltage of NMOS 13 be BV.sub.dss, BV.sub.p, and BV.sub.N respectively. A typical relation between these breakdown voltages may be expressed as follows. EQU BV.sub.dss -BV.sub.p =BV.sub.N ( 3)
However, in diode 14, there is a parasitic bipolar transistor structure in which the cathode layer 84 acts as an emitter, anode layer 55 acts as a base, and n.sup.- -type epitaxial layer 3 and n.sup.+ -type substrate 2 act as a collector. Thus, the isolation breakdown voltage of diode 14 is a collector-emitter breakdown voltage V.sub.CEO of the parasitic bipolar transistor. Generally, EQU V.sub.CEO =0.4.about.0.7.times.V.sub.CBO ( 4)
where, V.sub.CBO is a collector-base breakdown voltage.
In the case of the power IC as shown in FIG. 4, therefore, the following relation is established. EQU V.sub.CBO =BV.sub.dss -BV.sub.P =BV.sub.N ( 5)
Accordingly, the breakdown voltage of the power IC is determined by the breakdown voltage V.sub.CEO and this breakdown voltage is between 0.4 and 0.7 times the breakdown voltage BV.sub.dss.
In the conventional power circuit, in order to mitigate lowering of the breakdown voltage due to its dependence of V.sub.CEO, resistivity .rho. and thickness t.sub.2 of the n.sup.- -type epitaxial layer are large to set V.sub.CEO high. The large resistivity .rho. and thickness t.sub.2, however, results in a large R.sub.epi, as shown in expression (2). A large R.sub.epi results in a large on-state resistance R.sub.on, as shown in expression (1). Thus, in the conventional circuit there is a trade-off between on-state resistance and breakdown voltage.